Magnetoresistive random access memory (MRAM) devices are well known in the art and come in a variety of forms. To achieve large integrated MRAM arrays, the individual MRAM bits and their associated sense and drive transistors and circuitry should be formed on a common substrate. FIG. 1 shows a simplified schematic cross-sectional view of memory device 20 comprising magnetoresistive random access memory (MRAM) bit 22 integrated with at least one drive/sense transistor 23 on common N-type semiconductor (SC) substrate 24 (e.g., silicon), according to the prior art. Transistor 23 has P-well region 25 in which are formed N+ source and drain regions 26. For convenience of description, it is assumed that N+ region 262 functions as a source and N+ region 261 functions as a drain. Control gate 28 overlies gate dielectric (e.g., silicon oxide) 29 above channel region 27 between source 262 and drain 261. Conductive vias 301, 302, 303 (collectively 30) couple source and drain regions 26 and gate 28 to portions 331, 332, 333 of conductor 33, also referred to as “metal-1”, that is, source region 262 to portion 332, drain region 261 to portion 331 and gate 28 to portion 333. Conductive via 34 couples portion 332 of metal-1 33 to second conductor 35, also referred to as “metal-2”. Metal-1 33 and metal-2 35 are supported by dielectric 43. Conductive via 36 couples metal-2 35 to MRAM bit 22. MRAM bit 22 comprises, for example, antiferromagnet layer 37 in contact with via 36 and surmounted successively by pinned layer 38, spacer or barrier layer 39 and free magnetic layer 40. Non-magnetic conductive cap electrode 41 is provided on free magnetic layer 40. Non-magnetic conductive cap electrode 41 is in turn coupled to further interconnect layer 42 also referred to as “metal-3”. Spacer or barrier layer 39 may be either a non-magnetic conductive spacer layer, in which case MRAM bit 22 is referred to as a “spin valve” (SV) device, or a thin tunneling dielectric layer, in which case MRAM bit 22 is referred to as “spin tunnel junction” (STJ) device. MRAM bit 22 and metal-3 42 are supported by dielectric 44. Either composition of layer 39 is useful, and the present invention does not depend upon the exact nature of MRAM bit 22. For convenience of description it is assumed that spin momentum transfer is used to program MRAM bit 22 and that layer 39 is a dielectric tunneling layer, but this is not intended to be limiting. Such structures and programming mode are well known in the art.
It is often the case that the materials and processes needed to form an array of MRAM bits 22 are different than the materials and processes needed to form the array of associated drive/sense transistors (e.g., multiple transistors 23) and circuitry (e.g., vias 30, metal-1 33, vias 34, metal-2 35, various connections to gates 28, etc.), collectively referred to as the “drive/sense circuits” 21.
It has been customary in the past to form the MRAM devices after the associated drive/sense circuits 21 have been completed. This gives rise to at least two important problems that can have a significant negative affect on the cost of integrated MRAM arrays. First, the number of manufacturing steps needed to form the prior art integrated MRAM array is approximately equal to the total number of steps to individually form the associated drive/sense transistors and circuits, plus the steps needed to form the MRAM bits and their interconnections. Since the manufacturing cost and yield is proportional to the number of manufacturing steps and their complexity, it is advantageous to make the manufacturing process more efficient by reducing the number of manufacturing steps needed to form the combination of drive/sense circuits and MRAM bits. Second, the historic approach of building the MRAM bits separately from the drive/sense circuits 21 also tends to increase the total chip area occupied by the MRAM array, thereby also increasing the unit cost of such arrays since there are fewer die per wafer. Thus, prior art MRAM arrays are said to also be space inefficient. Accordingly there is an ongoing need for more space and process efficient structures and methods in which MRAM bits are more closely integrated with their associated drive/sense devices and circuits.
Accordingly, it is desirable to provide more space and process efficient structures and methods for forming the MRAM bits and associated drive/sense circuits. In addition, it is desirable that the improved structures and methods be simple, rugged and reliable, and further, that the MRAM bits included therein be formed in a manner compatible with semiconductor device and integrated circuit structures on the same substrate. It is further desirable that the improved MRAM structures and method reduce the number of required process steps and more fully integrate the MRAM bits with the associated drive/sense devices and circuits in order to more efficiently use the available chip area and thereby further improve the manufacturing yield and reduce the cost. Other desirable features and characteristics of the invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.